1728 search results - page 143 / 346 » The Size of Power Automata |
164
click to vote
ISCA
2007
IEEE
16 years 29 days ago
2007
IEEE
From multiprocessor scale-up to cache sizes to the number of reorder-buffer entries, microarchitects wish to reap the benefits of more computing resources while staying within po...
169
click to vote
RSP
2003
IEEE
15 years 12 months ago
2003
IEEE
We describe cache architecture, intended for prototype-oriented IC platforms, that automatically finds the best cache configuration for a particular application. The cache itself ...
171
click to vote
WSC
2004
15 years 8 months ago
2004
One feature of many naturally occurring or engineered complex systems is tremendous variability in event sizes. To account for it, the behavior of these systems is often described...
178
click to vote
TWC
2008
15 years 6 months ago
2008
In this paper, the problem of choosing constellation size and transmit power that minimizes the energy-per-goodbit in a frequency-flat, long-term static fading channel is considere...
182
click to vote
CODES
2007
IEEE
16 years 1 months ago
2007
IEEE
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...