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» The Size of Power Automata
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ASPDAC
2007
ACM
156views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Archit
- This paper presents a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for fram...
Zahid Khan, Tughrul Arslan
FPL
2008
Springer
141views Hardware» more  FPL 2008»
15 years 8 months ago
An analytical model describing the relationships between logic architecture and FPGA density
This paper describes an analytical model, based principally on Rent's Rule, that relates logic architectural parameters to the area efficiency of an FPGA. In particular, the ...
Andrew Lam, Steven J. E. Wilton, Philip Heng Wai L...
CORR
2010
Springer
37views Education» more  CORR 2010»
15 years 6 months ago
A Unique 10 Segment Display for Bengali Numerals
Segmented display is widely used for efficient display of alphanumeric characters. English numerals are displayed by 7 segment and 16 segment display. The segment size is uniform ...
Muhammad Abul Kalam Azad, Rezwana Sharmeen, Shabbi...
176
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LATA
2009
Springer
16 years 1 months ago
Termination of Priority Rewriting
Introducing priorities on rules in rewriting increases their expressive power and helps to limit computations. Priority rewriting is used in rule-based programming as well as in f...
Isabelle Gnaedig
IPPS
2007
IEEE
16 years 1 months ago
Peak-Performance DFA-based String Matching on the Cell Processor
The security of your data and of your network is in the hands of intrusion detection systems, virus scanners and spam filters, which are all critically based on string matching. ...
Daniele Paolo Scarpazza, Oreste Villa, Fabrizio Pe...