Sciweavers

1728 search results - page 110 / 346
» The Size of Power Automata
Sort
View
CGO
2005
IEEE
16 years 11 hour ago
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh ...
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
15 years 11 months ago
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
Anoop Iyer, Diana Marculescu
ISPD
2007
ACM
124views Hardware» more  ISPD 2007»
15 years 8 months ago
Accurate power grid analysis with behavioral transistor network modeling
In this paper, we propose fast and efficient techniques to analyze the power grid with accurate modeling of the transistor network. The solution techniques currently available for...
Anand Ramalingam, Giri Devarayanadurg, David Z. Pa...
JETC
2008
127views more  JETC 2008»
15 years 4 months ago
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...
Yong Zhan, Sachin S. Sapatnekar
DAC
2005
ACM
16 years 7 months ago
Hardware speech recognition for user interfaces in low cost, low power devices
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer