Reducing power consumption has become a key goal for systemon-a-chip (SOC) designs. Fast and accurate power estimation is needed early in the design process, since power reduction...
Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been...
Multi-million gate System-on-Chip (SoC) designs increasingly rely on Intellectual Property (IP) blocks. However, due to technology scaling the leakage power consumption of the IP ...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...
Power consumption is a troublesome design constraint for emergent systems such as IBM’s BlueGene /L. If current trends continue, future petaflop systems will require 100 megawat...
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...