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ICCD
2005
IEEE
159views Hardware» more  ICCD 2005»
16 years 8 days ago
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
LCPC
2005
Springer
16 years 5 days ago
Loop Selection for Thread-Level Speculation
Thread-level speculation (TLS) allows potentially dependent threads to speculatively execute in parallel, thus making it easier for the compiler to extract parallel threads. Howeve...
Shengyue Wang, Xiaoru Dai, Kiran Yellajyosula, Ant...
ICDCS
2003
IEEE
15 years 12 months ago
Protecting BGP Routes to Top Level DNS Servers
—The Domain Name System (DNS) is an essential part of the Internet infrastructure and provides fundamental services, such as translating host names into IP addresses for Internet...
Lan Wang, Xiaoliang Zhao, Dan Pei, Randy Bush, Dan...
SIGGRAPH
2010
ACM
15 years 11 months ago
Street slide: browsing street level imagery
Systems such as Google Street View and Bing Maps Streetside enable users to virtually visit cities by navigating between immersive 360◦ panoramas, or bubbles. The discrete moves...
Johannes Kopf, Billy Chen, Richard Szeliski, Micha...
LPAR
2001
Springer
15 years 11 months ago
Local Conditional High-Level Robot Programs
When it comes to building robot controllers, highlevel programming arises as a feasible alternative to planning. The task then is to verify a high-level program by finding a lega...
Sebastian Sardiña