7742 search results - page 214 / 1549 » The Robustness of Level Sets |
161
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WCRE
2002
IEEE
15 years 11 months ago
2002
IEEE
As new computer architectures are developed to exploit large-scale data-level parallelism, techniques are needed to retarget legacy sequential code to these platforms. Sequential ...
187
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ISPD
1999
ACM
15 years 11 months ago
1999
ACM
There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and dom...
188
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ISCA
1998
IEEE
15 years 11 months ago
1998
IEEE
Pipeline flushes due to branch mispredictions is one of the most serious problems facing the designer of a deeply pipelined, superscalar processor. Many branch predictors have bee...
110
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ASPDAC
1998
ACM
15 years 11 months ago
1998
ACM
—An AND-OR-EXOR network, where the output EXOR gate has only two inputs, is one of the simplest three-level architecture. This network realizes an EXOR of two sum-of-products exp...
175
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HPCA
1997
IEEE
15 years 10 months ago
1997
IEEE
Fast Ethernet and ATM are two attractive network technologies for interconnecting workstation clusters for parallel and distributed computing. This paper compares network interfac...