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ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
16 years 1 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
ISQED
2008
IEEE
153views Hardware» more  ISQED 2008»
16 years 1 months ago
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding
Clock meshes have found increasingly wide applications in today’s high-performance IC designs. The inherent routing redundancies associated with clock meshes lead to improved cl...
Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jia...
NDSS
2008
IEEE
16 years 1 months ago
Usable PIR
In [22] we showed that existing single-server computational private information retrieval (PIR) protocols for the purpose of preserving client access patterns leakage are orders o...
Peter Williams, Radu Sion
220
Voted
ANSS
2007
IEEE
16 years 1 months ago
Vehicular Mobility Simulation for VANETs
During the last few years, continuous progresses in wireless communications have opened new research fields in computer networking, aimed at extending data networks connectivity ...
Marco Fiore, Jérôme Härri, Fethi...
CODES
2007
IEEE
16 years 1 months ago
HW/SW co-design for Esterel processing
We present a co-synthesis approach that accelerates reactive software processing by moving the calculation of complex expressions into external combinational hardware. The startin...
Sascha Gädtke, Claus Traulsen, Reinhard von H...
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