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SBACPAD
2008
IEEE
249views Hardware» more  SBACPAD 2008»
16 years 1 months ago
Processing Neocognitron of Face Recognition on High Performance Environment Based on GPU with CUDA Architecture
This work presents an implementation of Neocognitron Neural Network, using a high performance computing architecture based on GPU (Graphics Processing Unit). Neocognitron is an ar...
Gustavo Poli, José Hiroki Saito, Joã...
ICCAD
2005
IEEE
95views Hardware» more  ICCAD 2005»
16 years 3 months ago
Application-specific network-on-chip architecture customization via long-range link insertion
Networks-on-Chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either complete...
Ümit Y. Ogras, Radu Marculescu
IPPS
2006
IEEE
16 years 22 days ago
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
Grigoris Dimitroulakos, Michalis D. Galanis, Const...
FPL
2009
Springer
161views Hardware» more  FPL 2009»
15 years 11 months ago
A multi-FPGA architecture for stochastic Restricted Boltzmann Machines
Although there are many neural network FPGA architectures, there is no framework for designing large, high-performance neural networks suitable for the real world. In this paper, ...
Daniel L. Ly, Paul Chow
TMC
2010
89views more  TMC 2010»
15 years 5 months ago
SIP-Based IMS Signaling Analysis for WiMax-3G Interworking Architectures
—The third-generation partnership project (3GPP) and 3GPP2 have standardized the IP multimedia subsystem (IMS) to provide ubiquitous and access network-independent IP-based servi...
Arslan Munir, Ann Gordon-Ross