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DATE
2009
IEEE
119views Hardware» more  DATE 2009»
16 years 1 months ago
On-chip communication architecture exploration for processor-pool-based MPSoC
— MPSoC is evolving towards processor-pool (PP)-based architectures, which employ hierarchical on-chip network for inter- and intra-PP communication. Since the design space of PP...
Young-Pyo Joo, Sungchan Kim, Soonhoi Ha
CCS
2007
ACM
16 years 23 days ago
Shunting: a hardware/software architecture for flexible, high-performance network intrusion prevention
Stateful, in-depth, inline traffic analysis for intrusion detection and prevention is growing increasingly more difficult as the data rates of modern networks rise. Yet it remai...
José M. González, Vern Paxson, Nicho...
CODES
2000
IEEE
15 years 11 months ago
Compaan: deriving process networks from Matlab for embedded signal processing architectures
This paperpresents the Compaantool that automatically transforms a nestedloopprogram written in Matlab into a processnetwork specification. The processnetworkmodelof computation...
Bart Kienhuis, Edwin Rijpkema, Ed F. Deprettere
ISCA
2003
IEEE
112views Hardware» more  ISCA 2003»
15 years 12 months ago
A Pipelined Memory Architecture for High Throughput Network Processors
Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. In this paper we focus on the design of a programmable architecture...
Timothy Sherwood, George Varghese, Brad Calder
PREMI
2005
Springer
16 years 2 days ago
Artificial Neural Network Engine: Parallel and Parameterized Architecture Implemented in FPGA
In this paper we present and analyze an artificial neural network hardware engine, its architecture and implementation. The engine was designed to solve performance problems of the...
Milene Barbosa Carvalho, Alexandre Marques Amaral,...