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TPDS
2002
105views more  TPDS 2002»
15 years 6 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills
INFOCOM
2010
IEEE
15 years 5 months ago
Two Samples are Enough: Opportunistic Flow-level Latency Estimation using NetFlow
—The inherent support in routers (SNMP counters or NetFlow) is not sufficient to diagnose performance problems in IP networks, especially for flow-specific problems where the ...
Myungjin Lee, Nick G. Duffield, Ramana Rao Kompell...
VTC
2010
IEEE
168views Communications» more  VTC 2010»
15 years 4 months ago
Cross-Layer Adaptive H.264/AVC Streaming over IEEE 802.11e Experimental Testbed
—In recent years, the rapid development of wireless communication allows us to enjoy more multimedia services via wireless network. However, due to lack of QoS support and charac...
Cheng-Han Mai, Yin-Cheng Huang, Hung-Yu Wei
ICOODB
2010
171views Database» more  ICOODB 2010»
15 years 4 months ago
Data Model Driven Implementation of Web Cooperation Systems with Tricia
Abstract. We present the data modeling concepts of Tricia, an opensource Java platform used to implement enterprise web information systems as well as social software solutions inc...
Thomas Büchner, Florian Matthes, Christian Ne...
DAC
2002
ACM
16 years 7 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
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