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PPL
2008
185views more  PPL 2008»
15 years 6 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
TOMACS
1998
140views more  TOMACS 1998»
15 years 6 months ago
Technical Note: A Hierarchical Computer Architecture Design and Simulation Environment
architectures at multiple levels of abstraction, encompassing both hardware and software. It has five modes of operation (Design, Model Validation, Build Simulation, Simulate Syste...
Paul S. Coe, Fred W. Howell, Roland N. Ibbett, Lau...
TMC
2008
159views more  TMC 2008»
15 years 5 months ago
Protecting Location Privacy with Personalized k-Anonymity: Architecture and Algorithms
Continued advances in mobile networks and positioning technologies have created a strong market push for location-based applications. Examples include location-aware emergency resp...
Bugra Gedik, Ling Liu
IPPS
2010
IEEE
15 years 4 months ago
Scalable multi-pipeline architecture for high performance multi-pattern string matching
Multi-pattern string matching remains a major performance bottleneck in network intrusion detection and anti-virus systems for high-speed deep packet inspection (DPI). Although Aho...
Weirong Jiang, Yi-Hua Edward Yang, Viktor K. Prasa...
ICDCS
2009
IEEE
15 years 4 months ago
The Case for Spam-Aware High Performance Mail Server Architecture
The email volume per mailbox has largely remained low and unchanged in the past several decades, and hence mail server performance has largely remained a secondary issue. The stee...
Abhinav Pathak, Syed Ali Raza Jafri, Y. Charlie Hu