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CODES
2006
IEEE
16 years 25 days ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
MICRO
2003
IEEE
116views Hardware» more  MICRO 2003»
16 years 1 days ago
Universal Mechanisms for Data-Parallel Architectures
Data-parallel programs are both growing in importance and increasing in diversity, resulting in specialized processors targeted at specific classes of these programs. This paper ...
Karthikeyan Sankaralingam, Stephen W. Keckler, Wil...
RTAS
1997
IEEE
15 years 11 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
HPCA
2008
IEEE
16 years 7 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
HICSS
2007
IEEE
122views Biometrics» more  HICSS 2007»
16 years 1 months ago
Enterprise Information Architecture (EIA): Assessment of Current Practices in Malaysian Organizations
In this paper we described the findings based on a research study on current Enterprise Information Architecture (EIA) practices in Malaysian organizations. Ten organizations from...
Rafidah Abd. Razak, Zulkhairi Md. Dahalin, Rohaya ...