6271 search results - page 303 / 1255 » The RACE network architecture |
164
click to vote
CGO
2005
IEEE
16 years 10 days ago
2005
IEEE
Register allocation is one of the most important optimizations a compiler performs. Conventional graphcoloring based register allocators are fast and do well on regular, RISC-like...
149
click to vote
IWIA
2005
IEEE
16 years 9 days ago
2005
IEEE
1 Intrusion detection in MANETs is challenging because these networks change their topologies dynamically; lack concentration points where aggregated traffic can be analyzed; utili...
196
click to vote
IPPS
2003
IEEE
15 years 12 months ago
2003
IEEE
ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design c...
155
click to vote
ASPDAC
2009
ACM
15 years 11 months ago
2009
ACM
– The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Mo...
155
click to vote
JSSPP
1995
Springer
15 years 10 months ago
1995
Springer
In this paper, we describe a new job scheduling class, called \Time Space Sharing Scheduling" (TSSS) for dynamically partitionable parallel machines. As an instance of TSSS, ...