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MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
16 years 1 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
ISSADS
2005
Springer
16 years 6 days ago
Database System Architecture - A Walk Through Time: From Centralized Platform to Mobile Computing - Keynote Address
Classical distributed database systems monolithically offer distribution transparency and higher performance. This is made possible by making data available and closer to the appl...
Ali R. Hurson, Yu Jiao
JCM
2008
118views more  JCM 2008»
15 years 6 months ago
New Receiver Architecture Based on Optical Parallel Interference Cancellation for the Optical CDMA
Optical Code Division Multiple Access (OCDMA) is considered as the strongest candidates for the future high speed optical networks due to the large bandwidth offered by the system,...
N. Elfadel, A. A. Aziz, E. Idriss, A. Mohammed, N....
TPDS
2008
134views more  TPDS 2008»
15 years 6 months ago
Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On th...
Ricardo Fernández Pascual, José M. G...
INFOCOM
2007
IEEE
16 years 1 months ago
On the Optimality and Interconnection of Valiant Load-Balancing Networks
— The Valiant Load-Balancing (VLB) design has been proposed for a backbone network architecture that can efficiently provide predictable performance under changing traffic matr...
Moshe Babaioff, John Chuang