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FPL
2009
Springer
152views Hardware» more  FPL 2009»
15 years 11 months ago
Clock gating architectures for FPGA power reduction
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
Safeen Huda, Muntasir Mallick, Jason H. Anderson
RSP
1998
IEEE
15 years 11 months ago
Reusable Architecture Templates and Automatic Specification Mapping for the Efficient Implementation of ATM Protocols
This paper presents an algorithm for the automatic mapping of problem specifications to existing architecture templates. The proposed methodology supports the combination of exist...
Nikos S. Voros, Evaggelinos P. Mariatos, Michael K...
CCS
1998
ACM
15 years 11 months ago
A Security Architecture for Computational Grids
State-of-the-art and emerging scientific applications require fast access to large quantities of data and commensurately fast computational resources. Both resources and data are ...
Ian T. Foster, Carl Kesselman, Gene Tsudik, Steven...
RAS
2010
137views more  RAS 2010»
15 years 5 months ago
Development of complex robotic systems using the behavior-based control architecture iB2C
This paper presents a development methodology for complex robotic systems using the behavior-based control architecture iB2C (integrated Behavior-Based Control). It is shown how a...
Martin Proetzsch, Tobias Luksch, Karsten Berns
USENIX
2004
15 years 8 months ago
A Network Positioning System for the Internet
Network positioning has recently been demonstrated to be a viable concept to represent the network distance relationships among Internet end hosts. Several subsequent studies have...
T. S. Eugene Ng, Hui Zhang