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ACSD
2007
IEEE
94views Hardware» more  ACSD 2007»
16 years 16 days ago
Sarir: A Rebeca to mCRL2 Translator
We describe a translation from Rebeca, an actorbased language, to mCRL2, a process algebra enhanced with data types. The main motivation is to exploit the verification tools and ...
Hossein Hojjat, Marjan Sirjani, Mohammad Reza Mous...
IPPS
2007
IEEE
16 years 15 days ago
Rethinking Automated Synthesis of MPSoC Architectures
Emerging heterogeneous multiprocessors will have custom memory and bus architectures that must balance resource sharing and system partitioning to meet cost constraints. We propos...
Brett H. Meyer, Donald E. Thomas
IPPS
2007
IEEE
16 years 15 days ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson
IPPS
2007
IEEE
16 years 15 days ago
C++ based System Synthesis of Real-Time Video Processing Systems targeting FPGA Implementation
Implementing real-time video processing systems put high requirements on computation and memory performance. FPGAs have proven to be effective implementation architecture for thes...
Najeem Lawal, Mattias O'Nils, Benny Thörnberg
ISPA
2007
Springer
16 years 10 days ago
Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap ...
Tarik Saidani, Lionel Lacassagne, Samir Bouaziz, T...