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ISCAS
2007
IEEE
141views Hardware» more  ISCAS 2007»
16 years 1 months ago
Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes
Abstract— We analyze the decoding algorithm for regular timeinvariant LDPC convolutional codes as a 3D signal processing scheme and derive several parallelization concepts, which...
Emil Matús, Marcos B. S. Tavares, Marcel Bi...
UML
2005
Springer
16 years 9 days ago
Simplifying Transformations of OCL Constraints
Abstract. With the advent of Model Driven Architecture, OCL constraints are no longer necessarily written by humans. They can be part of models that emerge from a chain of transfor...
Martin Giese, Daniel Larsson
TAL
2004
Springer
16 years 5 days ago
Automatic Acquisition of Transfer Rules from Translation Examples
In our research, we have developed a transfer-based machine translation architecture for the translation from Japanese into German. One main feature of the system is the fully auto...
Werner Winiwarter
ICSE
2009
IEEE-ACM
15 years 11 months ago
Synthesis of timed behavior from scenarios in the Fujaba Real-Time Tool Suite
Based on a well-defined component architecture the tool supports the synthesis of so-called real-time statecharts from timed sequence diagrams. The two step synthesis process add...
Stefan Henkler, Joel Greenyer, Martin Hirsch, Wilh...
DAC
1996
ACM
15 years 11 months ago
Software Development in a Hardware Simulation Environment
Concurrent verification of hardware and software as part of the development process can shorten the time to market of complex systems. The objectives of the Virtual CPU approach i...
Benny Schnaider, Einat Yogev