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» The Primacy of Process Architecture
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DATE
2004
IEEE
105views Hardware» more  DATE 2004»
15 years 10 months ago
Time-Energy Design Space Exploration for Multi-Layer Memory Architectures
This paper presents an exploration algorithm which examines execution time and energy consumption of a given application, while considering a parameterized memory architecture. Th...
Radoslaw Szymanek, Francky Catthoor, Krzysztof Kuc...
ASPDAC
2001
ACM
100views Hardware» more  ASPDAC 2001»
15 years 10 months ago
Low power implementation of a turbo-decoder on programmable architectures
Low Power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal ar...
Frank Gilbert, Alexander Worm, Norbert Wehn
EUROCRYPT
2000
Springer
15 years 10 months ago
Cox-Rower Architecture for Fast Parallel Montgomery Multiplication
Abstract. This paper proposes a fast parallel Montgomery multiplication algorithm based on Residue Number Systems (RNS). It is easy to construct a fast modular exponentiation by ap...
Shin-ichi Kawamura, Masanobu Koike, Fumihiko Sano,...
ARVLSI
1997
IEEE
151views VLSI» more  ARVLSI 1997»
15 years 10 months ago
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...
Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun
DSN
2005
IEEE
15 years 8 months ago
SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors
Soft errors are a growing concern for processor reliability. Recent work has motivated architecture-level studies of soft errors since the architecture can mask many raw errors an...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...