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LION
2010
Springer
188views Optimization» more  LION 2010»
15 years 11 months ago
Grapheur: A Software Architecture for Reactive and Interactive Optimization
Abstract This paper proposes a flexible software architecture for interactive multiobjective optimization, with a user interface for visualizing the results and facilitating the s...
Mauro Brunato, Roberto Battiti
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
15 years 11 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
RTSS
1989
IEEE
15 years 10 months ago
A Distributed Fault Tolerant Architecture for Nuclear Reactor Control and Safety Functions
A new fault tolerant architecture that provides tolerance to a broad scope of hardware, software, and communications faults is being developed. This architecture relies on widely ...
Myron Hecht, J. Agron, S. Hochhauser
DAC
2009
ACM
15 years 10 months ago
NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core
Traditional debug methodologies are limited in their ability to provide debugging support for many-core parallel programming. Synchronization problems or bugs due to race conditio...
Chi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen, Alan P...
CODES
2004
IEEE
15 years 10 months ago
Efficient exploration of on-chip bus architectures and memory allocation
Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and map...
Sungchan Kim, Chaeseok Im, Soonhoi Ha