2045 search results - page 76 / 409 » The Practice of Instructional Design: The Process and Its Ap... |
168
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DAC
2004
ACM
16 years 7 months ago
2004
ACM
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...
175
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IPPS
2006
IEEE
16 years 6 days ago
2006
IEEE
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
164
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ESTIMEDIA
2006
Springer
15 years 9 months ago
2006
Springer
Parallelization of embedded software is often desirable for power/performance-related considerations for computation-intensive applications that frequently occur in the signal-pro...
159
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HPCA
1999
IEEE
15 years 10 months ago
1999
IEEE
Control independence has been put forward as a significant new source of instruction-level parallelism for future generation processors. However, its performance potential under p...
199
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ACMMSP
2006
ACM
16 years 4 days ago
2006
ACM
Most operating systems enforce process isolation through hardware protection mechanisms such as memory segmentation, page mapping, and differentiated user and kernel instructions....