Sciweavers

3806 search results - page 259 / 762
» The Power of Process
Sort
View
ASPDAC
2006
ACM
135views Hardware» more  ASPDAC 2006»
16 years 17 days ago
Robust analytical gate delay modeling for low voltage circuits
— Sakurai-Newton (SN) delay metric [1] is a widely used closed form delay metric for CMOS gates because of simplicity and reasonable accuracy. Nevertheless it can be shown that t...
Anand Ramalingam, Sreekumar V. Kodakara, Anirudh D...
ATS
2005
IEEE
144views Hardware» more  ATS 2005»
16 years 6 days ago
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing
—Test application at reduced power supply voltage (low-voltage testing) or reduced temperature (low-temperature testing) can improve the defect coverage of a test set, particular...
Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Bec...
DATE
2005
IEEE
118views Hardware» more  DATE 2005»
16 years 6 days ago
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms
In this work we consider battery powered portable systems which either have Field Programmable Gate Arrays (FPGA) or voltage and frequency scalable processors as their main proces...
Jawad Khan, Ranga Vemuri
ICN
2005
Springer
16 years 1 days ago
An Energy Constrained Multi-hop Clustering Algorithm for Wireless Sensor Networks
A wireless sensor network is a new kind of wireless Ad-Hoc network consisting of a large number of small low cost, power constrained sensors deployed in a large area for gathering...
Navin Kumar Sharma, Mukesh Kumar
ICCAD
2003
IEEE
325views Hardware» more  ICCAD 2003»
15 years 12 months ago
Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading
While performance, area, and power constraints have been the driving force in designing current communication-enabled embedded systems, post-fabrication and run-time adaptability ...
Brian Swahn, Soha Hassoun