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ISPASS
2006
IEEE
16 years 22 days ago
Automatic testcase synthesis and performance model validation for high performance PowerPC processors
The latest high-performance IBM PowerPC microprocessor, the POWER5 chip, poses challenges for performance model validation. The current stateof-the-art is to use simple hand-coded...
Robert H. Bell Jr., Rajiv R. Bhatia, Lizy K. John,...
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
16 years 22 days ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
BMCBI
2010
89views more  BMCBI 2010»
15 years 6 months ago
Detection of gene pathways with predictive power for breast cancer prognosis
Background: Prognosis is of critical interest in breast cancer research. Biomedical studies suggest that genomic measurements may have independent predictive power for prognosis. ...
Shuangge Ma, Michael R. Kosorok
INFOCOM
2006
IEEE
16 years 23 days ago
A Power-Saving Multi-Radio Multi-Channel MAC Protocol for Wireless Local Area Networks
— Opportunistic spectrum access and adaptive power management are effective techniques to improve throughput, delay performance, and energy efficiency for wireless networks. In ...
Jianfeng Wang, Yuguang Fang, Dapeng Oliver Wu
ASPDAC
2007
ACM
95views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier"
In this Paper, we describe the various low power techniques for mobile application SoCs based on the integrated platform "UniPhier". To minimize SoC power dissipation, h...
Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasa...