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ASPDAC
2005
ACM
93views Hardware» more  ASPDAC 2005»
15 years 8 months ago
Power minimization for dynamic PLAs
—Dynamic programmable logic arrays (PLAs) which are built of the NOR–NOR structure, have been very popular in high performance design because of their high-speed and predictabl...
Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, ...
NIPS
2007
15 years 8 months ago
Managing Power Consumption and Performance of Computing Systems Using Reinforcement Learning
Electrical power management in large-scale IT systems such as commercial datacenters is an application area of rapidly growing interest from both an economic and ecological perspe...
Gerald Tesauro, Rajarshi Das, Hoi Chan, Jeffrey O....
ICCAD
2009
IEEE
89views Hardware» more  ICCAD 2009»
15 years 4 months ago
Decoupling capacitance efficient placement for reducing transient power supply noise
Decoupling capacitance (decap) is an efficient way to reduce transient noise in on-chip power supply networks. However, excessive decap may cause more leakage power, chip resource...
Xiaoyi Wang, Yici Cai, Qiang Zhou, Sheldon X.-D. T...
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
16 years 3 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
186
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SIGCOMM
2009
ACM
16 years 1 months ago
Game action based power management for multiplayer online game
Current mobile devices embrace a wide range of functionalities including high speed network support, hardware accelerated 3D graphics, and multimedia capabilities. These capabilit...
Bhojan Anand, Akkihebbal L. Ananda, Mun Choon Chan...