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DFT
2005
IEEE
83views VLSI» more  DFT 2005»
16 years 5 days ago
An ILP Formulation for Yield-driven Architectural Synthesis
Data flow graph dominant designs, such as communication video and audio applications, are common in today’s IC industry. In these designs, the datapath resources (e.g., adders,...
Zhaojun Wo, Israel Koren, Maciej J. Ciesielski
ECRTS
2005
IEEE
16 years 5 days ago
Improved Schedulability Analysis of EDF on Multiprocessor Platforms
Multiprocessor hardware platforms are now being considered for embedded systems, due to their high computational power and little additional cost when compared to single processor...
Marko Bertogna, Michele Cirinei, Giuseppe Lipari
ECRTS
2005
IEEE
16 years 5 days ago
A WCET-Oriented Static Branch Prediction Scheme for Real Time Systems
Branch prediction mechanisms are becoming commonplace within current generation processors. Dynamic branch predictors, albeit able to predict branches quite accurately in average,...
François Bodin, Isabelle Puaut
GLVLSI
2005
IEEE
67views VLSI» more  GLVLSI 2005»
16 years 5 days ago
Energy recovery clocked dynamic logic
Energy recovery clocking results in significant energy savings in clock distribution networks as compared to conventional squarewave clocking. However, since energy recovery clock...
Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen,...
GLVLSI
2005
IEEE
152views VLSI» more  GLVLSI 2005»
16 years 5 days ago
A high speed and leakage-tolerant domino logic for high fan-in gates
Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose a new domino circuit for high fan-in ...
Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peirav...