This paper proposes a 0.5V / 100MHz / sub-5mW-operated 1-Mbit SRAM cell architecture which uses an overVCC grounded data storage (OVGS) scheme. The key target of OVGS is to minimi...
Abstract. Recent trend in high-performance computing focuses on networks of workstations (NOWs) as a way ofrealizing cost-effective parallel machines. This has been due to the avai...
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path...
Abstract. In many-core CMP architectures, the cache coherence protocol is a key component since it can add requirements of area and power consumption to the final design and, there...
The IBM Cell Broadband Engine (BE) is a multicore processor with a PowerPC host processor (PPE) and 8 synergic processor engines (SPEs). The Cell BE architecture is designed to im...
Tamer F. Rabie, Hashir Karim Kidwai, Fadi N. Sibai