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» The Power of Comparative Reasoning
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VTS
2008
IEEE
77views Hardware» more  VTS 2008»
16 years 1 months ago
Test-Pattern Ordering for Wafer-Level Test-During-Burn-In
—Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significa...
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
GLOBECOM
2007
IEEE
16 years 29 days ago
Iterative Decoding of Concatenated Channel Coding and Trellis Shaping Based on Markov Model
—The trellis shaping (TS) is an effective technique not only for average power reduction of high-order QAM signals, but also for peak power reduction of band-limited single-carri...
Makoto Tanahashi, Hideki Ochiai
GLOBECOM
2007
IEEE
16 years 29 days ago
Design of High Throughput Scheduled Mesh Networks: A Case for Directional Antennas
Abstract— Scheduled wireless mesh networks (WMNs) represent an important paradigm in the development of high speed wireless access networks. As a consequence of [1], it can be sh...
Skanda N. Muthaiah, Aravind Iyer, Aditya Karnik, C...
ICC
2007
IEEE
140views Communications» more  ICC 2007»
16 years 28 days ago
Design of Time and Frequency Domain Pilots for Generalized Multicarrier Systems
— By the generalized multi-carrier (GMC) principle a unified framework to describe various multi-carrier as well as single carrier approaches is established. In this paper1 the ...
Chan-Tong Lam, Gunther Auer, Florence Danilo-Lemoi...
FPL
2007
Springer
100views Hardware» more  FPL 2007»
16 years 23 days ago
Clock-Aware Placement for FPGAs
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...
Julien Lamoureux, Steven J. E. Wilton