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DAC
1998
ACM
15 years 10 months ago
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
Ganesh Lakshminarayana, Niraj K. Jha
CASES
2007
ACM
15 years 10 months ago
A low power front-end for embedded processors using a block-aware instruction set
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since inst...
Ahmad Zmily, Christos Kozyrakis
EMSOFT
2008
Springer
15 years 7 months ago
On the interplay of dynamic voltage scaling and dynamic power management in real-time embedded applications
Dynamic Voltage Scaling (DVS) and Dynamic Power Management (DPM) are two popular techniques commonly employed to save energy in real-time embedded systems. DVS policies aim at red...
Vinay Devadas, Hakan Aydin
TCOM
2008
128views more  TCOM 2008»
15 years 6 months ago
Cross-Layer Rate and Power Adaptation Strategies for IR-HARQ Systems over Fading Channels with Memory: A SMDP-Based Approach
Abstract--Incremental-redundancy hybrid automatic repeatrequest (IR-HARQ) schemes are proposed in several wireless standards for increased throughput-efficiency and greater reliabi...
Ashok K. Karmokar, Dejan V. Djonin, Vijay K. Bharg...
TCAD
2011
15 years 1 months ago
Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
—Pre-bond testing of 3-D stacked integrated circuits (ICs) involves testing each individual die before bonding. The overall yield of 3-D ICs improves with pre-bond testability be...
Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung K...