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ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
15 years 11 months ago
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
Anoop Iyer, Diana Marculescu
TWC
2010
15 years 1 months ago
Cooperative Decode-and-Forward ARQ Relaying: Performance Analysis and Power Optimization
Abstract--In this paper we develop a new analytical methodology for the evaluation of the outage probability of cooperative decode-and-forward (DF) automatic-repeat-request (ARQ) r...
Sangkook Lee, Weifeng Su, Stella N. Batalama, John...
DAC
2004
ACM
16 years 7 months ago
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
Ashish Srivastava, Dennis Sylvester, David Blaauw
DAC
2005
ACM
16 years 7 months ago
Hardware speech recognition for user interfaces in low cost, low power devices
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer
DATE
2009
IEEE
132views Hardware» more  DATE 2009»
16 years 1 months ago
Power and performance of read-write aware Hybrid Caches with non-volatile memories
—Caches made of non-volatile memory technologies, such as Magnetic RAM (MRAM) and Phase-change RAM (PRAM), offer dramatically different power-performance characteristics when com...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Yu...