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DAC
2005
ACM
16 years 7 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
ICC
2007
IEEE
185views Communications» more  ICC 2007»
16 years 21 days ago
Maximal Lifetime Rate and Power Allocation for Sensor Networks with Data Distortion Constraints
— We address a lifetime maximization problem for a single-hop wireless sensor network where multiple sensors encode and communicate their measurements of a Gaussian random source...
James C. F. Li, Subhrakanti Dey, Jamie S. Evans
ICDCSW
2005
IEEE
15 years 12 months ago
Probability Based Power Aware Error Resilient Coding
Error resilient encoding in video communication is becoming increasingly important due to data transmission over unreliable channels. In this paper, we propose a new power-aware e...
Minyoung Kim, Hyunok Oh, Nikil D. Dutt, Alexandru ...
SIGMETRICS
2003
ACM
150views Hardware» more  SIGMETRICS 2003»
15 years 11 months ago
Conductance and congestion in power law graphs
It has been observed that the degrees of the topologies of several communication networks follow heavy tailed statistics. What is the impact of such heavy tailed statistics on the...
Christos Gkantsidis, Milena Mihail, Amin Saberi
ECSQARU
2003
Springer
15 years 11 months ago
Morphing the Hugin and Shenoy-Shafer Architectures
Abstract. The Hugin and Shenoy–Shafer architectures are two variations on the jointree algorithm, which exhibit different tradeoffs with respect to efficiency and query answeri...
James D. Park, Adnan Darwiche