Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
In this paper we address the problem of managing heterogeneous workloads in a virtualized data center. We consider two different workloads: transactional applications and long-ru...
David Carrera, Malgorzata Steinder, Ian Whalley, J...
The emergence of heterogeneous many core architectures presents a unique opportunity for delivering order of magnitude performance increases to high performance applications by ma...
The process of creating e-learning contents using reusable learning objects (LOs) can be broken down in two sub-processes: LOs finding and LO sequencing. Although semiautomatic to...
—Control design of Self-servo Track Writer (SSTW) has become an important issue in Hard Disk Drive research. This paper discusses the error propagation problem in SSTW control. A...