16188 search results - page 2866 / 3238 » The Optimal PAC Algorithm |
188
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ICCAD
2007
IEEE
16 years 3 months ago
2007
IEEE
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
174
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the red...
157
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate perfor...
154
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ICCAD
2005
IEEE
16 years 3 months ago
2005
IEEE
Large-scale process fluctuations in nano-scale IC technologies suggest applying high-order (e.g., quadratic) response surface models to capture the circuit performance variations....
160
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ICCAD
2003
IEEE
16 years 3 months ago
2003
IEEE
This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit tim...