16188 search results - page 2846 / 3238 » The Optimal PAC Algorithm |
146
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DAC
2009
ACM
16 years 7 months ago
2009
ACM
Post-silicon validation has recently drawn designers' attention due to its increasing impacts on the VLSI design cycle and cost. One key feature of the post-silicon validatio...
183
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DAC
2008
ACM
16 years 7 months ago
2008
ACM
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
150
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DAC
2008
ACM
16 years 7 months ago
2008
ACM
The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and...
171
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DAC
2008
ACM
16 years 7 months ago
2008
ACM
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
185
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DAC
2008
ACM
16 years 7 months ago
2008
ACM
: Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future universal memory. It combines the desirable attributes of current memory technologies such as SRA...