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JVA
2006
IEEE
16 years 15 days ago
Optimal Monte Carlo Algorithms
Ivan Todor Dimov
ISCAS
2005
IEEE
158views Hardware» more  ISCAS 2005»
16 years 2 days ago
Designing optimized pipelined global interconnects: algorithms and methodology impact
— As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of lat...
Vidyasagar Nookala, Sachin S. Sapatnekar