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SLIP
2009
ACM
16 years 28 days ago
Floorplan-based FPGA interconnect power estimation in DSP circuits
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic
DATE
2004
IEEE
151views Hardware» more  DATE 2004»
15 years 10 months ago
Dynamic Voltage and Cache Reconfiguration for Low Power
Given a set of real-time tasks scheduled using the earliest deadline first (EDF) algorithm, we discuss two techniques for reducing power consumption while meeting all timing requi...
André C. Nácul, Tony Givargis
PACS
2000
Springer
121views Hardware» more  PACS 2000»
15 years 10 months ago
Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power
Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadvertently will lead to an exponential increase in leakage power dissipation. In this work we ex...
Stefanos Kaxiras, Zhigang Hu, Girija J. Narlikar, ...
FAST
2003
15 years 7 months ago
Modeling Hard-Disk Power Consumption
Excessive power consumption is a major barrier to the market acceptance of hard disks in mobile electronic devices. Studying and reducing power consumption, however, often involve...
John Zedlewski, Sumeet Sobti, Nitin Garg, Fengzhou...
WCE
2007
15 years 7 months ago
Power Flow Modelling of a Self-excited Induction Generator
—This paper presents power flow models of a self-excited induction generator. These models are used for steady-state power flow calculation in electric power systems in which a g...
Thanatchai Kulworawanichpong, P. Sangsarawut