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ISCA
2007
IEEE
117views Hardware» more  ISCA 2007»
16 years 21 days ago
ReCycle: : pipeline adaptation to tolerate process variation
Process variation affects processor pipelines by making some stages slower and others faster, therefore exacerbating pipeline unbalance. This reduces the frequency attainable by t...
Abhishek Tiwari, Smruti R. Sarangi, Josep Torrella...
ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
16 years 11 days ago
The design and implementation of a low-latency on-chip network
— Many of the issues that will be faced by the designers of multi-billion transistor chips may be alleviated by the presence of a flexible global communication infrastructure. I...
Robert D. Mullins, Andrew West, Simon W. Moore
DAMON
2006
Springer
15 years 10 months ago
Processing-in-memory technology for knowledge discovery algorithms
The goal of this work is to gain insight into whether processingin-memory (PIM) technology can be used to accelerate the performance of link discovery algorithms, which represent ...
Jafar Adibi, Tim Barrett, Spundun Bhatt, Hans Chal...
VLSI
2010
Springer
15 years 4 months ago
Synchronous elasticization: Considerations for correct implementation and MiniMIPS case study
—Latency insensitivity is a promising design paradigm in the nanometer era since it has potential benefits of increased modularity and robustness to variations. Synchronous elas...
Eliyah Kilada, Shomit Das, Kenneth S. Stevens
TC
2010
15 years 1 months ago
A Counter Architecture for Online DVFS Profitability Estimation
Dynamic voltage and frequency scaling (DVFS) is a well known and effective technique for reducing power consumption in modern microprocessors. An important concern though is to est...
Stijn Eyerman, Lieven Eeckhout