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» The Observational Power of Clocks
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2004
ACM
15 years 12 months ago
A Performance and Scalability Analysis of the BlueGene/L Architecture
This paper is structured as follows. Section 2 gives an architectural description of BlueGene/L. Section 3 analyzes the issue of “computational noise” – the effect that the o...
Kei Davis, Adolfy Hoisie, Greg Johnson, Darren J. ...
MICRO
2009
IEEE
134views Hardware» more  MICRO 2009»
16 years 1 months ago
A case for dynamic frequency tuning in on-chip networks
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
Asit K. Mishra, Reetuparna Das, Soumya Eachempati,...
INFOCOM
2007
IEEE
16 years 25 days ago
Can Retransmissions of Superexponential Documents Cause Subexponential Delays?
— Consider a generic data unit of random size L that needs to be transmitted over a channel of unit capacity. The channel dynamics is modeled as an on-off process {(Ai, Ui)}i≥1...
Predrag R. Jelenkovic, Jian Tan
ICS
2009
Tsinghua U.
16 years 1 months ago
High-performance regular expression scanning on the Cell/B.E. processor
Matching regular expressions (regexps) is a very common workload. For example, tokenization, which consists of recognizing words or keywords in a character stream, appears in ever...
Daniele Paolo Scarpazza, Gregory F. Russell
ARCS
2009
Springer
16 years 1 months ago
Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
Joseph Gebis, Leonid Oliker, John Shalf, Samuel Wi...