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ISCA
2003
IEEE
212views Hardware» more  ISCA 2003»
15 years 11 months ago
A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels
Trends in microprocessors of increasing die size and clock speed and decreasing feature sizes have fueled rapidly increasing performance. However, the limited improvements in DRAM...
Jinwoo Suh, Eun-Gyu Kim, Stephen P. Crago, Lakshmi...
SLIP
2003
ACM
15 years 11 months ago
Error-correction and crosstalk avoidance in DSM busses
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
Ketan N. Patel, Igor L. Markov
VLSID
2002
IEEE
192views VLSI» more  VLSID 2002»
15 years 11 months ago
Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems
à This paper addresses the problem of static and dynamic variable voltage scheduling of multi-rate periodic task graphs (i.e., tasks with precedence relationships) and aperiodic t...
Jiong Luo, Niraj K. Jha
ISPAN
2000
IEEE
15 years 11 months ago
Versatile Processor Design for Efficiency and High Performance
We present new architectural concepts for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D2 -CPU (Data-Driven processor) follows the natura...
Sotirios G. Ziavras
ISPD
1997
ACM
100views Hardware» more  ISPD 1997»
15 years 10 months ago
A pseudo-hierarchical methodology for high performance microprocessor design
- This paper reports on a highly effective methodology to construct complex high performance microprocessors. Critical aspects of the methodology include an integrated database for...
A. Bertolet, K. Carpenter, Keith M. Carrig, Albert...