1542 search results - page 136 / 309 » The Observational Power of Clocks |
163
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ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
Dynamic voltage scaling (DVS) is a technique that varies the supply voltage and clock frequency based on the computation load to provide desired performance with the minimal amoun...
177
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
— As clock frequencies exceed giga-Hertz, the extra power loss due to conductor surface roughness in interconnects and packagings is more evident and thus demands a proper accou...
165
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
Abstract—In this paper a programmable Forward Error Correction (FEC) IP for a DVB-S2 receiver is presented. It is composed of a Low-Density Parity Check (LDPC), a Bose-ChaudhuriH...
163
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—Interconnect structures significantly contribute to the delay, power consumption, and silicon area of modern reconfigurable architectures. The demand for higher clock frequencie...
183
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ASPDAC
2009
ACM
16 years 1 months ago
2009
ACM
— Recent advances in statistical timing analysis (SSTA) achieve great success in computing arrival times under variations by extending sum and maximum operations to random variab...