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DAC
2001
ACM
16 years 7 months ago
A True Single-Phase 8-bit Adiabatic Multiplier
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthy...
EXPCS
2007
15 years 10 months ago
The user in experimental computer systems research
Experimental computer systems research typically ignores the end-user, modeling him, if at all, in overly simple ways. We argue that this (1) results in inadequate performance eva...
Peter A. Dinda, Gokhan Memik, Robert P. Dick, Bin ...
ICCD
2005
IEEE
100views Hardware» more  ICCD 2005»
16 years 3 months ago
Temporal Decomposition for Logic Optimization
Traditional approaches for sequential logic optimization include (1) explicit state-based techniques such as state minimization, (2) structural techniques such as retiming, and (3...
Nathan Kitchen, Andreas Kuehlmann
FCCM
2007
IEEE
129views VLSI» more  FCCM 2007»
16 years 25 days ago
Automatic On-chip Memory Minimization for Data Reuse
FPGA-based computing engines have become a promising option for the implementation of computationally intensive applications due to high flexibility and parallelism. However, one...
Qiang Liu, George A. Constantinides, Konstantinos ...
ASPDAC
2006
ACM
118views Hardware» more  ASPDAC 2006»
16 years 14 days ago
A probabilistic analysis of pipelined global interconnect under process variations
— The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a ...
Navneeth Kankani, Vineet Agarwal, Janet Meiling Wa...