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ISCAS
2006
IEEE
79views Hardware» more  ISCAS 2006»
16 years 15 days ago
A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application
—In this paper, we propose a cost-effective and low-power 64-point fast Fourier transform (FFT)/inverse FFT (IFFT) architecture and chip adopting the retrenched 8-point FFT/IFFT ...
Chin-Teng Lin, Yuan-Chu Yu, Lan-Da Van
APCSAC
2005
IEEE
16 years 3 days ago
The Challenges of Massive On-Chip Concurrency
Moore’s law describes the growth in on-chip transistor density, which doubles every 18 to 24 months and looks set to continue for at least a decade and possibly longer. This grow...
Kostas Bousias, Chris R. Jesshope
CHES
2005
Springer
82views Cryptology» more  CHES 2005»
16 years 15 hour ago
Masking at Gate Level in the Presence of Glitches
Abstract. It has recently been shown that logic circuits in the implementation of cryptographic algorithms, although protected by “secure” random masking schemes, leak side-cha...
Wieland Fischer, Berndt M. Gammel
MICRO
2002
IEEE
173views Hardware» more  MICRO 2002»
15 years 11 months ago
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
Christoforos E. Kozyrakis, David A. Patterson
DATE
1999
IEEE
162views Hardware» more  DATE 1999»
15 years 10 months ago
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
Robert P. Dick, Niraj K. Jha