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VTS
2005
IEEE
106views Hardware» more  VTS 2005»
16 years 12 days ago
Segmented Addressable Scan Architecture
This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consum...
Ahmad A. Al-Yamani, Erik Chmelar, Mikhail Grinchuc...
IPPS
2002
IEEE
15 years 11 months ago
Eclipse: Heterogeneous Multiprocessor Architecture for Flexible Media Processing
Eclipse is a heterogeneous multiprocessor architecture for high-performance media processing, including highdefinition MPEG encoding/decoding. The scalable architecture framework ...
Martijn J. Rutten, Jos T. J. van Eijndhoven, Evert...
CONPAR
1992
15 years 11 months ago
Asynchronous Polycyclic Architecture
The Asynchronous Polycyclic Architecture (APA) is a new processor design for numerically intensive applications. APA resembles the VLIW architecture, in that it provides independen...
Geraldo Lino de Campos
SBIA
2000
Springer
15 years 10 months ago
Applying the ARTIS Agent Architecture to Mobile Robot Control
Abstract. The agent/multi-agent system paradigm is an important field of Artificial Intelligence. The use of this paradigm in real-world problems is one of the main lines of intere...
José Soler, Vicente Julián, Carlos C...
FPL
2008
Springer
117views Hardware» more  FPL 2008»
15 years 8 months ago
A versatile hardware architecture for a CFAR detector based on a linear insertion sorter
This paper presents a versatile hardware architecture that implements six variant of the CFAR detector based on linear and non-linear operations. Since some implemented CFAR detec...
Roberto Perez-Andrade, René Cumplido, Claud...