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PDP
2011
IEEE
14 years 10 months ago
Accelerating Parameter Sweep Applications Using CUDA
—This paper proposes a parallelization scheme for parameter sweep (PS) applications using the compute unified device architecture (CUDA). Our scheme focuses on PS applications w...
Masaya Motokubota, Fumihiko Ino, Kenichi Hagihara
DAC
2011
ACM
14 years 6 months ago
Modeling adaptive streaming applications with parameterized polyhedral process networks
The Kahn Process Network (KPN) model is a widely used modelof-computation to specify and map streaming applications onto multiprocessor systems-on-chips. In general, KPNs are dif...
Jiali Teddy Zhai, Hristo Nikolov, Todor Stefanov
CODES
2005
IEEE
16 years 12 days ago
Designing real-time H.264 decoders with dataflow architectures
High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...
Youngsoo Kim, Suleyman Sair
ACSAC
2002
IEEE
15 years 11 months ago
Security Architecture of the Austrian Citizen Card Concept
When admitting electronic media as a means for citizens to approach public authorities – i.e., when advancing official proceedings towards e-Government – security is an indisp...
Herbert Leitold, Arno Hollosi, Reinhard Posch
DAC
2001
ACM
16 years 7 months ago
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping
In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven m...
Jason Cong, Michail Romesis