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ASAP
2007
IEEE
118views Hardware» more  ASAP 2007»
15 years 8 months ago
Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers
This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...
Götz Kappen, S. el Bahri, O. Priebe, Tobias G...
ICASSP
2007
IEEE
15 years 8 months ago
SIFME: A Single Iteration Fractional-Pel Motion Estimation Algorithm and Architecture for HDTV Sized H.264 Video Coding
This paper presents a set of fast algorithm and VLSI architecture for HDTV-sized H.264 fractional motion estimation. To solve the long computational latency in HD-sized applicatio...
Tzu-Yun Kuo, Yu-Kun Lin, Tian-Sheuan Chang
ERSA
2006
282views Hardware» more  ERSA 2006»
15 years 8 months ago
SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture
Reconfigurable devices, such as FPGAs, introduce into the design workflow of embedded systems a new degree of freedom: the designer can have the system autonomously modify the fun...
Carlo Amicucci, Fabrizio Ferrandi, Marco D. Santam...
ICWS
2004
IEEE
15 years 8 months ago
A Semantic Web Services Enabled Web Portal Architecture
Web services technologies are emerging as a new approach for supporting e-Science and e-Engineering by providing access to heterogeneous computation resources and integration of d...
Xiaorong Xiang, Gregory R. Madey
SIGCOMM
2010
ACM
15 years 7 months ago
Architecture optimisation with Currawong
We describe Currawong, a tool to perform system software architecture optimisation. Currawong is an extensible tool which applies optimisations at the point where an application i...
Nicholas Fitzroy-Dale, Ihor Kuz, Gernot Heiser