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SASP
2009
IEEE
170views Hardware» more  SASP 2009»
16 years 1 months ago
Parade: A versatile parallel architecture for accelerating pulse train clustering
— In this paper, we present Parade, a novel and flexible parallel architecture for the deinterleaving of combined pulsetrains. This is a commonly performed task in various areas ...
Amin Ansari, Dan Zhang, Scott A. Mahlke
SI3D
1995
ACM
15 years 10 months ago
The Sort-First Rendering Architecture for High-Performance Graphics
Interactive graphics applications have long been challenging graphics system designers by demanding machines that can provide ever increasing polygon rendering performance. Anothe...
Carl Mueller
WSC
1998
15 years 8 months ago
A Workbench for Predicting the Performances of Distributed Object Architectures
The development of a Distributed Information System (DIS) can lead to critical bottlenecks because of the underlying architecture, which is becoming more and more complex. Todays ...
Sophie Dumas, Georges Gardarin
VLSISP
2008
106views more  VLSISP 2008»
15 years 6 months ago
Architecture Considerations for Multi-Format Programmable Video Processors
Many different video processor architectures exist. Its architecture gives a processor strength for a particular application. Hardwired logic yields the best performance/cost, but ...
Jonah Probell
IEEEPACT
2006
IEEE
16 years 22 days ago
Core architecture optimization for heterogeneous chip multiprocessors
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi