Sciweavers

9049 search results - page 1604 / 1810
» The New C Standard
Sort
View
VLSID
2004
IEEE
147views VLSI» more  VLSID 2004»
16 years 7 months ago
Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
Shabbir H. Batterywala, Narendra V. Shenoy
VLSID
2002
IEEE
207views VLSI» more  VLSID 2002»
16 years 7 months ago
Synthesis of High Performance Low Power Dynamic CMOS Circuits
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
Debasis Samanta, Nishant Sinha, Ajit Pal
HPCA
2007
IEEE
16 years 7 months ago
Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling
Performance gains in memory have traditionally been obtained by increasing memory bus widths and speeds. The diminishing returns of such techniques have led to the proposal of an ...
Brinda Ganesh, Aamer Jaleel, David Wang, Bruce L. ...
CHI
2004
ACM
16 years 7 months ago
Master usability scaling: magnitude estimation and master scaling applied to usability measurement
Master Usability Scaling (MUS) is a measurement method for developing a universal usability continuum based on magnitude estimation and master scaling. The universal usability con...
Mick McGee
POPL
2007
ACM
16 years 7 months ago
Specialization of CML message-passing primitives
Concurrent ML (CML) is a statically-typed higher-order concurrent language that is embedded in Standard ML. Its most notable feature is its support for first-class synchronous ope...
John H. Reppy, Yingqi Xiao
« Prev « First page 1604 / 1810 Last » Next »