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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
15 years 11 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
RTSS
2002
IEEE
15 years 11 months ago
The Space of Rate Monotonic Schedulability
Feasibility analysis of fixed priority systems has been widely studied in the real-time literature and several acceptance tests have been proposed to guarantee a set of periodic ...
Enrico Bini, Giorgio C. Buttazzo
SIGGRAPH
2000
ACM
15 years 11 months ago
Style machines
We approach the problem of stylistic motion synthesis by learning motion patterns from a highly varied set of motion capture sequences. Each sequence may have a distinct choreogra...
Matthew Brand, Aaron Hertzmann
PODC
1999
ACM
15 years 11 months ago
Liveness-Preserving Simulation Relations
We present a new approach for reasoning about liveness properties of distributed systems, represented as automata. Our approach is based on simulation relations, and requires reas...
Paul C. Attie
ICCV
1999
IEEE
15 years 11 months ago
3D Pose Tracking with Linear Depth and Brightness Constraints
This paper explores the direct motion estimation problem assuming that video-rate depth information is available, from either stereo cameras or other sensors. We use these depth m...
Michael Harville, Ali Rahimi, Trevor Darrell, Gail...
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