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DATE
2009
IEEE
113views Hardware» more  DATE 2009»
16 years 1 months ago
System-level process variability analysis and mitigation for 3D MPSoCs
Abstract—While prior research has extensively evaluated the performance advantage of moving from a 2D to a 3D design style, the impact of process parameter variations on 3D desig...
Siddharth Garg, Diana Marculescu
DAC
2006
ACM
16 years 7 months ago
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sh...
NANONET
2009
Springer
199views Chemistry» more  NANONET 2009»
15 years 11 months ago
Through Silicon Via-Based Grid for Thermal Control in 3D Chips
3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between...
José L. Ayala, Arvind Sridhar, Vinod Pangra...
VRML
2006
ACM
16 years 16 days ago
A case for 3D streaming on peer-to-peer networks
One of the most serious issues holding back the widespread of 3D contents on Internet has been their inaccessibility due to large data volume. Many compression and progressive tra...
Shun-Yun Hu
DAC
2004
ACM
16 years 7 months ago
Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics
Capacitance extraction is an important problem that has been extensively studied. This paper presents a significant improvement for the fast multipole accelerated boundary element...
Shu Yan, Vivek Sarin, Weiping Shi