Sciweavers

5100 search results - page 845 / 1020
» The Linear Complexity of a Graph
Sort
View
ICCAD
2008
IEEE
116views Hardware» more  ICCAD 2008»
16 years 3 months ago
Optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link example
—Connecting system-level performance models with circuit information has been a long-standing problem in analog/mixed-signal front-ends, like radios and high-speed links. High-sp...
Ranko Sredojevic, Vladimir Stojanovic
ICCAD
2008
IEEE
125views Hardware» more  ICCAD 2008»
16 years 3 months ago
A succinct memory model for automated design debugging
— In today’s complex SoC designs, verification and debugging are becoming ever more crucial and increasingly timeconsuming tasks. The prevalence of embedded memories adds to t...
Brian Keng, Hratch Mangassarian, Andreas G. Veneri...
ICCAD
2006
IEEE
124views Hardware» more  ICCAD 2006»
16 years 3 months ago
A linear-time approach for static timing analysis covering all process corners
Abstract—Manufacturing process variations lead to circuit timing variability and a corresponding timing yield loss. Traditional corner analysis consists of checking all process c...
Sari Onaissi, Farid N. Najm
ICCAD
2006
IEEE
125views Hardware» more  ICCAD 2006»
16 years 3 months ago
Leveraging protocol knowledge in slack matching
Stalls, due to mis-matches in communication rates, are a major performance obstacle in pipelined circuits. If the rate of data production is faster than the rate of consumption, t...
Girish Venkataramani, Seth Copen Goldstein
ICCAD
2003
IEEE
113views Hardware» more  ICCAD 2003»
16 years 3 months ago
Retiming with Interconnect and Gate Delay
In this paper, we study the problem of retiming of sequential circuits with both interconnect and gate delay. Most retiming algorithms have assumed ideal conditions for the non-lo...
Chris C. N. Chu, Evangeline F. Y. Young, Dennis K....