We highlight several fundamental challenges to designing highperformance integrated circuits in nanometer-scale technologies (i.e. drawn feature sizes < 100 nm). Dynamic power ...
The design of any application on a configurable System-on-a-Chip (SoC) like Atmel's FPSLIC is subject to a lot of constraints stemming from requirements of the application an...
Jens Bieger, Sorin A. Huss, Michael Jung, Stephan ...
To be able to enlarge a digital image from a single frame preserving the perceptive cues is a relevant research issue. The best algorithms take into account the presence of edges ...
Sebastiano Battiato, Giovanni Gallo, Filippo Stanc...
Hybrid nanoelectronics are emerging as one viable option to sustain the Moore’s Law after the CMOS scaling limit is reached. One main design challenge in hybrid nanoelectronics ...
—Due to the stringent computational capabilities of low-cost RFID tags, many lightweight authentication protocols have been proposed recently aiming to achieve secure authenticat...