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ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
16 years 12 days ago
A High Throughput String Matching Architecture for Intrusion Detection and Prevention
Network Intrusion Detection and Prevention Systems have emerged as one of the most effective ways of providing security to those connected to the network, and at the heart of alm...
Lin Tan, Timothy Sherwood
WOSP
2005
ACM
16 years 11 days ago
Performance evaluation of UML software architectures with multiclass Queueing Network models
Software performance based on performance models can be applied at early phases of the software development cycle to characterize the quantitative behavior of software systems. We...
Simonetta Balsamo, Moreno Marzolla
MICRO
2010
IEEE
140views Hardware» more  MICRO 2010»
15 years 4 months ago
Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories
Emerging non-volatile memory technologies such as phase change memory (PCM) promise to increase storage system performance by a wide margin relative to both conventional disks and ...
Adrian M. Caulfield, Arup De, Joel Coburn, Todor I...
SIGOPS
2011
255views Hardware» more  SIGOPS 2011»
15 years 1 months ago
Bridging functional heterogeneity in multicore architectures
Heterogeneous processors that mix big high performance cores with small low power cores promise excellent single– threaded performance coupled with high multi–threaded through...
Dheeraj Reddy, David A. Koufaty, Paul Brett, Scott...
DATE
1999
IEEE
113views Hardware» more  DATE 1999»
15 years 11 months ago
Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems
This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed m...
William Fornaciari, Donatella Sciuto, Cristina Sil...